There is mention of a BIT tutorial, but I didn't see one. Recently I realized that 65xx parts that lacked the immediate-mode BIT instruction (for testing flag bits) could make up for it by using 8 zero-page constants for each bit of a byte. This would allow testing several bits of the accumulator in succession without constantly reloading the accumulator.

Regarding the tutorial on compare instructions, I didn't see any mention of optimizing A <= n and A > n comparisons, where n is a constant, which would otherwise require two branches (because two status bits are involved in the condition). These can be optimized to A < n + 1 and A >= n + 1, respectively.

I still get confused about how the carry is set, since it's opposite what I'm used to on other CPUs. I was thinking of adding opcode aliases bge and blt for unsigned comparisons. I just looked more closely and the 6502's behavior makes sense; subtraction is implemented by adding the two's complement of the subtrahend to the minuend, which results in a carry when the minuend isn't less than the subtrahend.

(The obscurity of the names for the terms of subtraction crack me up)