Commodore PET 65816 CPU card
This a PET 65816 CPU card! It speeds up your PET to up to 10MHz. In fact it's a 6502 replacement card and could be used in other 6502-based computers as well. The board uses a 65816 CPU that runs at up to 10MHz, plus a Xilinx CPLD as logic glue. It includes up to 1MByte fast RAM (run at CPU speed) plus up to 512k parallel Flash ROM (in-system programmable), that can be used as boot ROM.
The interface itself is, in fact, pretty simple. It is a board that is plugged in the 6502 CPU socket of the PET. On the board there is the CPU, the CPLD logic, the new clock generator (50MHz), some few support parts, as well as two 512k static RAM and one 512k Flash RAM chip. The board is all-through-hole - i.e. no SMD parts! I call that a feature in these days.
The prototype has been tested with my CS/A65 computer, in the MMU board - which is easier to handle when you have to change things often. But it also now runs in the CBM8296. Tests with other PETs will follow.
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Table of content
I tried to repair a PET 4032 machine, that seems to have a memory problem. So I put in the 65816 board, with some boot code in the ROM, to run the PET in the 65816 board only. The result can be seen in the gallery, the PET runs at 10 MHz.
The boot code consists of the original 4032 (non-CRTC) ROMs plus some init code that copies the ROM contents from the board's ROM (i.e. not from the PET's original ROMs, that could be broken!) to fast RAM, and runs the system completely from the fast RAM. Only I/O is used and I was lucky that this works on my 4032, so I can use - and debug - the machine even with programs from the disk drive.
The code in the file below builds a
PDEBUG PET binary, that
when run, programs the boot ROM of the 65816 board. It assumes a 128k
Atmel Flash PROM for the write algorithm, as does the
|petdebug.tar.gz(PET 4032 test ROM)|
Here are some small tests that test the various features of the board.
Note that building them requires the
xa cross assembler, using
-w switch to enable 65816 code, as well as
from the VICE emulator package to build the BASIC parts.
Here is a description of the different tests (by subdirectory):
- benchmark - builds the
BENCHbenchmark program used to check the speed of the various settings. Builds from the
BENCH.basicBASIC source as well as
- eichtest - builds the burn-in test that, at its start, shows how fast the system
actually works (uses screen interrupts to determine system speed, so works
on my 2 MHz PET replica as well. Builds the
LOOPCommodore PET BASIC executable from
- maptest - some mapping tests.
COPYcopies 4k data from the system memory mirror at $e0xxxx to bank 0.
GOFASTcopies the system from slow memory over to the fast RAM mirror, and switches to it.
MAPTESTcompares the slow memory with the system memory mirror at $e0xxxx.
- modes - builds the
GOSLOWprograms that move execution to either fast RAM or back into slow memory.
GOFASTis updated compared to the maptest version though.
- progrom - programs the ROM to run a "GOFAST" functionality directly on reset,
as a boot rom. If you program your on-board ROM with this
PGOFASTcode, and set the bootrom jumper, the system will automatically boot into fast mode.(Edit: the programming algorithm in
proglib.a65has problems with larger blocks - better use the
|x816tests-1.0.tgz(Feature test suite)|
This is the VHDL code for the board. It is packaged as the XILINX ISE Webpack (v11.1) directory. Included in this directory is a "testbench" directory with some simulation test runs. Requires Linux with ghdl and GTKWave installed, then look into the Makefile.
Version 1.7.1 just has an updated testsuite.
|PET816_1.7.1.tar.bz2(Archive of the XILINX ISE Webpack CPLD logic - includes VHDL source, JED binary file, as well as a testbench. )|
|PET816_1.7.tar.bz2(Archive of the XILINX ISE Webpack CPLD logic - includes VHDL source, JED binary file, as well as a testbench. )|
|PET816_1.5.tar.bz2(Archive of the XILINX ISE Webpack CPLD logic - includes VHDL source, JED binary file, as well as a testbench. )|
|PET816_1.0.tar.bz2(Archive of the XILINX ISE Webpack CPLD logic - includes VHDL source, JED binary file, as well as a testbench. )|
|imgs/gtkwave.png(Sample screenshot of the timing simulation in the testbench)|
|This board is an update on the 1.2A, and only contains a few small changes: Two delay loops that can be used in the VHDL code have been added. Also an "official" diagnostics pin has been added too, to get easy access to a signal "exported" from the CPLD.|
|This board has been only barely tested|
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