Description for CS/A CPU65, version 1.2
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whatsit	: CPU + MMU
I/O	: MMU at $ff0-$fff
Mem	: --


This is the CPU board with an MMU to extend the 6502 address space
to 1 MByte. Having the MMU block diagram in mind, it's still pretty
straightforward...

Bus interface

IC7 is the CPU, which should be a 2MHz version for 1MHz system clock,
or a 4MHz version for 2MHz system clock - the MMU eats some address
setup time, which means we need a faster CPU.
IC11, 12 and 13 make up the bus drivers. 
IC16 is the bus driver for the MMU-mapped address lines A12-A19.
IC10 drives the clock lines. 

Timing generation

The CPU board generates all necessary clock signals. the 16MHz clock
is taken directly from the clock generator. J2 decides if the divider
IC9 gets 16 MHz or 8 MHz (QA) to divide by 8 to get the system clock (QD).
It is nevertheless possible to drive the CPU from the bus, using J3.
Then J4 must be open, of course. 

2Phi2 is generated by taking the normal Phi2 CPU output, delaying it
considerably, and XOR-ing with the Phi2 signal again. This way
after each transition of Phi2 we get a high signal of a certain length
on 2Phi2. I use this signal as a /CAS signal on the video card.

Select lines

IC14 is an 8 bit comparator which detects the fixed-address I/O space
at $e*** (J1 can make it $E800-$Efff). The output pin 19 is or'ed
with the inverted /IOINH bus signal, which can disable internal
I/O area selection. The result is inverted and put to the /MEMSEL 
output. One half of IC3 is then used to assert /IOSEL when either
the internal I/O selection is asserted or the external /EXTIO is
low. 
This way one can disable the I/O area at CPU address space and map
it somewhere else (must be on another card) by asserting /EXTIO
when accessing another memory location.

MMU access

Please note that, except for the CPU address line mapping (MA* -> MO*)
the complete MMU interface is on the bus side of the CPU bus buffers.
This way the MMU looks completely like any other I/O device
in the I/O area. IC17 selects the appropriate I/O area for the MMU.

One half of IC3 forms a RS-flip-flop that is reset when the /RES
line goes active, i.e. at a CPU reset. The MMU then goes to 
pass mode, i.e. it passes MA0-3 to MO8-11, setting all other MO* lines
to zero. Only ofter the first write access to the MMU registers
the flip-flop is set and /MM becomes active, putting the MMU 
into map mode. Then MA* are translated to MO0-11, using the register
contents. So the first write to the MMU should make sure that
the code the CPU is executing at this moment is not mapped away...

External bus master

With the /BE signal the bus drivers can be disabled. This signal is 
not synchronized, so the external bus master must do it itself.
The normal operation for an external bus master to get the
bus should be:

- assert RDY		-> CPU stops after at least three cycles
- wait three cycles	-> CPU has definitely stopped
- assert /BE 		-> ok, bus is yours.

... do your business

- release /BE 
- release Sync 

I have not looked up during which part of the CPU cycle these transitions
have to occur, nor have I ever tried this.

Bugs

I consider it a bug that /IOSEL is not an open-collector line that 
can be pulled by an external mapping card itself. Then /EXTIO could
be removed. But this is not really important, is it?