Description for CS/A CPU65, version 1.3
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whatsit	: CPU + MMU
I/O	: MMU at $ff0-$fff and $f70-$f7f
Mem	: --


This is the CPU board with an MMU to extend the 6502 address space
to 1 MByte. Having the MMU block diagram in mind, it's still pretty
straightforward...

This is the 'diff' to the version 1.2 description.

The new feature in this version is the possibility to map MMU pages
as write-protected. For this additional information an additional bit
for the MMU register is needed. The MMU has 12 bit registers, so this 
is not a problem. But the CPU can only write 8 bits at once, and all
are already used for the mapping information.

Therefore I use one of the address bits (A7) as additional data bit.
This means by writing to $eff* sets the additional bit to 1, writing
to $ef7* sets it to 0. When the MMU maps the address, the additional
output bit is then used to 

a) simulate a read access to the CS/A bus and
b) disable the data bus driver between the CPU and the bus.

When a write to a write-protected page occurs, the memory location
is read and not written to while the CPU still writes. The busses
do not collide as the driver between CPU data bus and CS/A data bus
is disabled.