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CS/A65 Video board

This board implements the a video board for the CS/A65 bus. The board uses 64k dynamic RAM that is accessed in a time-shared way, by the CPU at Phi2 high, and by the video at Phi2 low. Due to this interlock the board can display 40 columns a line at 1MHz system clock, and 80 columns a line at 2MHz system clock.

News:

Table of content

  • Driver
  • OS/A65 VDC hardware driver
    •
  • Board Revisions
  • 1.4A (untested)
  • 1.3E (prototype)
  • 1.3C (prototype with bugs)
    •
  • Block diagram
    •

    Driver

    OS/A65 VDC hardware driver

    This is the video-specific hardware part of the CS/A65 console driver. It provides the following methods:

    The video memory is memory-mapped into CPU address space, so the rest of the console driver (the hardware independent part) acts on this memory mapped video. The console can actually work in 40 columns (1MHz CPU clock) and 80 columns mode (2MHz CPU clock). This is detected by checking bit 7 of the freq variable.

    driver con_csa.a65(VDC driver excerpt)

    Board revisions

    Version: 1.4A

    Status: untested

    Notes

    msg In addition to the timing bugs this board implements a larger character ROM - now the character can be more than 8 pixels high. Also the crude circuit for the generation of the composite video signal is gone. Instead the video connector has an additional supply voltage pin, so the video plug can implement any better composite generation.
    warn This board is untested.
    msg Most of the TTL chips are 'ALS technology, but a few have to be 'LS for timing requirements: IC9 is a 74LS245 so that the data read from the RAM is held on the bus longer, as the CPU requires a certain hold time of that data. IC21 is a 'LS so that the delay between /RAS and /CAS is still long enough. IC9 may probably be an 'ALS04 as well, but never change a running system...

    Files

    desc csa_vdc_v1.4a-desc.txt
    parts csa_vdc_v1.4a-parts.txt
    schem csa_vdc_v1.4a-sch.png
    schem csa_vdc_v1.4a.sch
    layout csa_vdc_v1.4a-brd.png
    layout csa_vdc_v1.4a.brd

    Version: 1.3E

    Status: prototype

    Notes

    msg This board version is a redo of the original board, with the known bugs fixed.
    warn During testing with the PETCPU and new CS/A board - with 74ALS technology I decided to better restrict the timing on the video board (which was not the cause of the problem), so I patched the board. The results can be found in version 1.4.

    Files

    schem csa_vdc_v1.3e-sch.png
    schem csa_vdc_v1.3e.sch
    layout csa_vdc_v1.3e-lay.png
    layout csa_vdc_v1.3e.brd
    photo csa_vdc_v1.3e.jpg

    Version: 1.3C

    Status: prototype with bugs

    Notes

    msg This is the original video board.
    stop This schematics has a bug in the circuit to generate the shift register load signal. It went unnoticed as my prototype board was manually soldered.

    Files

    desc csavdcdesc.txt
    parts csavdcparts.txt
    schem csavdc.png
    schem csavdc.fig
    schem csavdc.ps.gz
    photo csavdc.jpg
    photo csavdcflip.jpg(The flipside - just for the fun of it... :-))

    Block diagram

    block diagram

    Block diagram of the vdc board. Only some relevant info is shown. It is actually a pretty simple design, if it were not for the timing... The CPU accesses the memory during Phi2 high, so then the BUSA0-15 and D0-7 are connected to the memory address and bus lines. During Phi2 low the video accesses the memory and thus RA0-13 is connected to the memory. The byte read for the video is latched and given to the character ROM as input. The CA0-2 lines select the correct scan line of the character in the character ROM. The output of the character ROM is then shifted out to the video output. More on how the CRTC works can be found on the CRTC page.