ALU as seen from the human brain


Now for something different.

This kind of ALU sometimes shows up in school books
and in HDL/VHDL source code.
It's the best approach to give the human brain a clue
about the inputs, the outputs, and the little things
that may happen between.
The big multiplexer at the right selects one of the functions:
A'&B', A'|B', A'+B', A' shiftet left/right, B' shiftet left/right.
Shifting is simply done by connecting A' and B' to the multiplexer,
for instance:
SHL (shift left) A' has carry_in->I5.0 A0->I5.1 A1-I5.2 A2->I5.3,
SHR (shift right) A' has A1->I7.0 A2 ->I7.1 A3->I7.2... carry_in->I7.7,
and so on.
Not shown in the schematic is the 8:1 carry output multiplexer,
that switches the carry output line to Adder, A0', A7', B0', B7',
according to the selected ALU function.

Note the AND/XOR gates between A and A', B and B'.
(The very obsolete 7487 had a 4 Bit AND/XOR combination,
for exactly that purpose.)

When inverting A and B, the logic functions change:
AND turns into NOR, OR turns into NAND.

A AND NOT B is done by choosing 'AND',
while inverting B with the XORs.

Arithmetic: when inverting A, A' becomes the one's complement of A,
and the Adder subtracts A from B. The high_active carry input/output
of the adder turns into a low_active borrow, as seen on the 6502 CPU.

Forcing the Adder carry input to 1 and setting A' to 0x00 will increment B.
Forcing the Adder carry input to 0 and setting A' to 0xff will decrement B.

There is nothing wrong with this block diagram.
But any attempt to wire/solder something like that with TTL chips
on bread board may always end up as a chaotic monstrousity.

For building an ALU with that functionality,
there is a more efficient approach.
Now to throw our Logic Unit into this game.


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(c) Dieter Mueller 2004