The MT15 instruction decoder/sequencer

MT15 is a CPU for architecture exploration.

The previous article described most of the hardware.

This article describes the part of MT15, that:

• decodes/executes the instructions
• reads/writes registers
• reads/writes memory
• controls the ALU
• updates the status register.

• Programmable Logic array
• Some basics
• PLA1: Sequencer/Bus_control
• PLA2: ALU address calculation/carry_in
• PLA3: ALU data calculation
• PLA4: Register read/write
• PLA5: Flag control
• Conclusion

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(c) Dieter Mueller 2005