Status Register

Now to describe the R0, the Status Register.

As in other CPUs, we have the Flags N,V,Z,C which are located in Bit 3..0
of the status register (actually two 7474).
Since we might want to load the status register with a value, there is a 74157
multiplexer in the inputs of those flipflops to load them from the bus in that case.

N,Z are always loaded simultaneously, so there is only one control signal LNZ
for both flags.

A simplified block diagram of the Status Register:

At the bottom of the box, we have the Flags N,V,Z,C as described above.

I4..I15 are signals from outside the CPU, latched into a 74574 while fetching
the next 32 Bit instruction word.

Then we have two 74273, which are cleared during reset.
They both can be written by software, and the outputs are available outside
the CPU (not shown in this block diagram).
There are two control signals available outside the CPU to disable a software
write to this latches, you might need that when implementing sort of a "memory
management unit" or a "user/supervisor mode" like with 68k.

Then we have a 16:1 multiplexer for testing the status of the N,V,Z,C Flag
and the inputs I4..15. Bit 3..0 from the 10 Bit instruction word controls the
multiplexer.
Buying a 74150 turned out to be very difficult, so we wired three 74151
together to work as a 74150.

The 32 Bit Status Register can be read by the CPU...
and this is, where trouble starts.

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