| "Label it computer porn to attract more readers.", |
| a friend from Italy did say...                     |
| ...It wasn't one of his best ideas.                |

If there would be a standard with FPGAs/CPLDs
as known from PALs/GALs, allowing me to select
between parts from different manufacturers with the
same Pin_out while still working with the same
(non_proprietary/open_source) software tools,
this project would not exist.

MT15 is a (mostly) transistorised CPU.

"Mostly" means, that 74xx chips are used in three places:
74LS164/74LS27 is used to generate the 4_phase_clock,
instruction decoder outputs are buffered with four 74HCT245,
and another four 74HCT245 work as buffer for the 16 Bit
address and data bus.

Everything else (Registers, Flags, ALU, instruction decoder etc.)
was built with BC847/BC857 low_frequency_transistors,
running with a 2.5 Volt supply.

Maximum power dissipation is around 13W (low power).

500 kHz 4_phase_clock, means a 2 us cycle, instructions
take 2 to 6 cycles.

Address range is 64 kWords (128 kBytes).

Contains circa 3000 low_frequency transistors, 3 EuroCents each.
(BC847/BC857 is a SMD_version of the well known BC547/BC557)

"Borrowed" CRT and Keyboard interface from my old M02 project.

MT15 modules:
View schematics as GIF images online (470 kB)
Download schematics and layouts for Eagle 3.55 as ZIP (200 kB)

2008: some crude software stuff, including an improvised emulator
and the source code of the monitor program which did run on the
MT15 hardware:

...Now for the pictures.

Test run:

front view

side view

command latch/flags/PLA

ALU/register slices and carry logic

complete CPU

display memory, starting at address $0400

power supply

CPU disconnected

CPU top

CPU bottom, "Sauerkraut" wiring

clock generation, top

clock generation, bottom

memory, top

memory, bottom: some more Sauerkraut.

A close look to MT15 Modules

8 expandable open_collector NANDs, 4 inputs each

4 Bit parallel carry (sort of a 74182)

1 Bit ALU slice

1 Bit register slice (4 registers)

4 transparent latches (Opcode, Flags, Sequencer)

"programmable" logic array, top (one of five)

"programmable" logic array, bottom

More technical details in the "articles" section:

(c) Dieter Mueller 2005