The 65k Project - Specifications
(C) 2010-2012 André Fachat
This page describes resp. links to the specifications for my 65k line of processors. For a reasoning why a feature is implemented as it is, see the Features discussion page.
The 65k will be available in different "sizes" - mainly in terms of register widths. For example options for 16 bit, 32 bit, and even 64 bit registers are defined. The first section will thus describe the options available.
The second section will then give links to the different models, their specifications and implementations.
Note that these tables are currently preliminary. The 65002 specifications are generated from the same source that generates the VHDL control tables. Therefore you will find the specifications directly in the af65xxx folders with the reference implementation.
Table of content
This section describes the different versions of the 65k processor
The 65k will be available in different "register widths". Register here means all address registers (stack pointer (SP), program counter (PC), base offset register (BR)), but also all data registers (AC, XR, YR). This does not include the status register for example. For details see the register model documentation. Address and Data registers will always have the same width to accomodate for address offsets computed in data registers.
The following options are available:
- 16 bit - a small extension to the original 6502 programming model, the PC stays 16 bit as it already is in the 6502.
- 32 bit - all data and address registers extended to 32 bit
- 64 bit - all data and address registers extended to 64 bit
The original register width for most of the registers is a byte. To use the registers with more than 8 bit a prefix opcode to the existing 8 bit opcodes is used. 2 bit of the prefix opcode are reserved for operation width, which allows to address registers as 8, 16, 32 or 64 bit.
The different register or operand widths are noted by a prefix. These prefixes are defined and used here:
|8||no prefix gives the 6502 8 bit behaviour|
|Q||64||Quadword (alternatively LL, but Q should be used)|
The 65k will be able to use different memory width options. I.e. the external memory interface of the processor can have different widths, from 8 bit over 16 bit to 32 bit. In the future it is possible to do a 64 bit memory interface.
Note that even though a processor variant has a wider memory interface, it can still use smaller width memory as well. I.e. a 32 bit wide memory interface can still handle 8 or 16 bit memory.
In the future there will be integer arithmetic in form of multiplication and division operations, possibly with other operations as well.
In the future there will be floating point arithmetic in form of addition, substruction, multiplication and division operations, possibly with other operations as well.
The 65k will optionally provide an MMU to translate virtual addresses (opcode effective addresses) into physical addresses. When the MMU is not included, virtual addresses are directly taken as physical addresses.
The 65k will provide a multicore option where two (or even more) cores are integrated into a single processor.
There will be a prefix bit that extends the operations that are not full width to a SIMD operations. For example, if this bit is set, and an 8 bit operation is performed on a 64 bit processor, the operation is performed simultaneously on all eight bytes of the 64 bit accumulator. Similarly for other combinations of register and operation widths.
The QUICK opcodes work with a separate prefix and implement the repeated execution of an existing opcode, e.g. "eight times INY"
The following table describes the different processor variants
|Variant||CPU width (W)||Memory width (MW)||Description||link|
|65002/WB||16||8||The /WB is the one that is closest to the original 6502. All of those are being created from the same VHDL source, with W and MW being generic parameters.||65002|
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