65816 board features

• Hardware Features
• • Jumpers and Connectors
• Software
• • Control Register
  • Memory Map
  • Speed Map
  • Clock register

Jumpers and Connectors

The board has a number of jumpers and connectors. The most important one is shown here:

• JP1: BOOTROM - when set to on, the on-board ROM is mapped into the lowest 64k address space upon reset, so the board can take the system over on power-up

Control Register

The CPLD implements a control register at the address $ExyF, where "xy" is determined by the jumper settings JP7/8/9. Unfortunately this register currently is write-only. Here is a description of the control register bits:

• Original ROMs disassembly

Memory Map

This section describes the memory map of the system. As there are some jumper settings that influence the memory map, it is best shown in a table.

Some things should probably be explained:

There is a FastRAM mirror in $f00000. This is used to copy the slow system bus memory to FastRAM. Normally the FastRAM is written through when the system bus is written to. But when copying the ROM from the 8296 to the FastRAM by copying the ROM in-place, the system hang: the 8296 has a write-only register at $fff0, writing the value read from the ROM there hangs the system. So to be sure you have to write to an unmirrored FastRAM - the mirror at $f00000.

The system bus mirror is there to access the slow system bus even when the lowest 64k are running in FastRAM. I made the mirror 16 times the 64k system bus, for a total of 1MByte, to stay "compatible" with my CS/A65 65816 CPU card. This may also be good for future expansions.

Speed Map

Although there is a dedicated "fast" and a dedicated "slow" bus (65816 vs. system bus), the CPU speed does not completely align with these borders. There are two types of access, "slow" and "fast". Slow is always synchronized with the system bus PHI2 clock. Fast accesses are independent from the system bus clock and the actual speed is determined by the clock register.

If the system bus accessed, of course the CPU is slowed down and synchronized with the slow system bus PHI2 clock, to perform the access. But also the ROM is accessed with the slow access method - so ordinary PROMs can be used.

The CPLD's control and clock registers are accessed from the CPU's fast bus, but the access is actually done slow, as the I/O address comparator is connected to the slow bus.

All that changes when SLOWCLK is set in the control register. Then all accesses, even to FastRAM, no matter what address are slow. This way you can easily use code that requires to runs at exactly the same clock than the original system.

Clock register

The CPLD not only implements a control register, but also a clock register at the address $ExyE, where "xy" is determined by the jumper settings JP7/8/9. Unfortunately also this register currently is write-only.

This clock register determines the speed of the actual fast accesses. Speed is determined by the lowest 5 bit, that work as a counter latch. In general the speed can be determined by calculating:

	FClk = 50MHz / (clklatch + 1)
	

Please note that you should not make the fast clock slower than the system clock, otherwise the system will hang!

Additionally the clock register contains the "fastmode" bit in bit 7. This bit is set by default. Its working is a bit difficult to explain. The board detects whether the next access is slow at a fixed point after system bus PHI2 going low. If fastmode is set, this detection is done very quickly, so that at most one fast half cycle fits before the detection. This means that the system clock can be up to 2MHz without loss of speed. But it also means that bogus cycles cannot be hidden. If fastmode is not set, the detection is done later, so that one and a half cycle fit in from PHI2 going low to this detection. This allows to hide bogus cycles within PHI1 of the system bus - but system clock can only be 1MHz, or the system will slow down (you can read more about it in the How it works page). Just remember that fastmode should be set on a 2MHz host system bus, and not on a 1MHz bus.