Differences of CRTC models
(C) 1999-2006 André Fachat
I have gathered together the differences between CRTC models from various sources. The docs to
- Rockwell 6545-1
- Motorola 6845, 6845-1, 68A45, 68A45-1, 68B45, 68B45-1
- Hitachi 46505
- Commodore 6545-1
- Rockwell 6545, 6545E
I will not go into details that are common to all chips. If you have further questions please refer to the CRTC documentation on http://www.zimmers.net/anonftp/pub/cbm/documents/chipdata/index.html and http://www.6502.org/documents/datasheets/.
Table of content
Although the pin naming is different, the pinout itself is the same for all chips, and all pins have the same meaning.
The Status register is read when the register select (RS) pin is low (when writing to this address, the index in the CRTC register file is written).
Commodore 6545-1, Rockwell 6545-1
Bits 0-4: not used
Bit 5: 0= scan currently not in vertical blanking portion
1= scan is currently in vertical blanking portion [1]
Bit 6: LPEN register full
0= goes to 0 whenever R16 or R17 are read
1= goes 1 when an LPEN strobe occurs
Bit 7: not used
Rockwell 6545
Bits 0-6: see Rockwell 6545-1
Bit 7: Update Ready
0= register 16 or 17 has been read by the CPU
1= an update strobe has been occurred.
Motorola 6845, 6845-1, Hitachi 46505
The status register is not mentioned at all...
[1] The Rockwell 6545 docs say that this bit "switches state at end of
last displayed rasterline" and "goes to a 0 five character clock times
before vertical retrace ends to ensure that critical timings for
refresh RAM is met."
The following registers are basically the same for all chips (see notes):
R0 Horizontal Total (-1)
R1 Horizontal Display
R2 Horizontal Sync position [1]
R4 Vertical total character lines (-1) (7 bit)
R5 Vertical total adjust rasterlines (5 bit)
R6 Vertical displayed character lines (7 bit)
R7 Vertical Sync position (7 bit) [1]
R9 Number of rasterlines per characterline (-1) [2]
R10 Cursor start rasterline + cursor mode control (5+2 bit)
R11 Cursor end rasterline (5 bit)
R12 Display start address high (6 bit) [3]
R13 Display start address low (8 bit) [3]
R14 Cursor address high (6 bit)
R15 Cursor address low (8 bit)
R16 Lightpen address high (6 bit)
R17 Lightpen address low (8 bit)
[1] Motorola states that "(Set data) = (Designated Data) - 1",
as it is known for R0, R4, and R9
[2] Commodore does not mention the "-1"
[3] It is possible to read R12 and R13 on Motorola CRTCs only.
All others can only read R14-R17.
Reading unused bits where possible reads a "0", which is, however, only explicitly stated in the Commodore docs.
The following items describe the major register file differences.
- R3, sync widths
Motorola 6845, Hitachi 46505: Bits 0-3: horizontal sync width in character times. Value=0 -> 16 Bits 4-7: unused Commodore 6545-1, Rockwell 6545 and 6545-1, Motorola 6845-1: Bits 0-3: horizontal sync width in character times. Value=0 -> 16 Bits 4-7: vertical sync width in rasterlines. Value=0 -> 16
- R8, Mode Control
Commodore 6545-1 and Rockwell 6545-1: Bit 0,1: Interlace control value of bits (1/0): x0: non-interlace [Rockwell says "Bit 0 must program to 0"] x1: invalid "do not use" [Rockwell says "not used"] Bit 2: 0 = straight binary addressing 1 = row/column addressing (see below) Bit 3: "Must Program to '0'" Bit 4: Display Enable Skew 0 = no delay 1 = delay Display Enable for one character clock cycle Bit 5: Cursor Enable Skew 0 = no delay 1 = delay Cursor Enable for one character clock cycle Bit 6,7: not used Rockwell 6545: Bits 0,1: Interlace control, see Motorola 6545 Bit 2: Addressing Mode, see Rockwell 6545-1 Bit 3: Refresh RAM access 0= shared memory access 1= transparent memory access Bit 4/5: display enable and cursor skew. See Rockwell 6545-1 Bit 6: Update Strobe (Transparent mode): 0= Pin 34 functions as memory address (RA4) 1= Pin 34 functions as update strobe Bit 7: Update/Read mode (Transparent mode): 0= Update occurs during horizontal and vertical blanking 1= Update interleaves during Phi2 portion of cycle Motorola 6845 and Hitachi 46505 Bit 0,1: Interlace control (see below) value of bits (1/0): x0: non-interlace, normal mode 01: interlace mode 11: interlace and video mode Bit 2-7: not used Motorola 6845-1 Bit 0-3: see Motorola 6845 Bit 4,5: Display Enable Skew value of bits (5/4): 00: no delay 01: delay Display Enable for one character clock cycle 10: delay Display Enable for two character clock cycles 11: not available Bit 6,7: Display Enable Skew value of bits (7/6): 00: no delay 01: delay Cursor Enable for one character clock cycle 10: delay Cursor Enable for two character clock cycles 11: not available
What can be learned already from this diagram? The Motorola 6845 (or the Hitachi 46505, but unlikely) was first and defined a basic set of features. Rockwell and Commodore then used the same derivation from the original design, while Motorola developed slightly different features. However, looking at the "must program to 0" entries, it seems Rockwell was not quick enough to implement the interlace modes and thus released an early version as 6545-1, before getting the full 6545 done, with some additional features.
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Last modified: 2013-11-02