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Dive into the retro feeling and build yourself a Commodore PET replica

Need more speed? Speed up your 6502 computer with this 10 MHz 6502 CPU replacement board

Interested in electronics design? Look at the design lesson I got from Bil Herd, the hardware designer of the C128

CS/A65 BIOS

This board implements basic memory and I/O functionality for the CS/A65 computer. The BIOS board complements the MMU CPU board in that it provides some RAM, ROM, and basic I/O (a RS232 interface, that is). It also has a special I/O port that allows the CPU to read the IRQ line, or the state of a pushbutton. Also a 50 Hz interrupt is provided that can be switched on and off with this port, as well as a system LED. The I/O mapping can be changed from the BIOS port as well. The older version 1 used a 6551 ACIA for the RS232 interface, but now I use a 16550 UART (with FIFO).

Table of content

  • Board Revisions
  • 3.0D (ok)
  • 3.0C (ok (for 32k RAM))
  • 3.0B (ok (for 32k RAM))
  • 2.0B (ok)
  • 1.x (ok)
  • Block diagram
  • Board revisions

    Version: 3.0D

    Status: ok

    Notes

    warn This board is definitely in for a re-layout, which will probably happen during the next change (>= 3.1), although nothing's planned yet.
    msg In this version the 512k RAM IC does not get the power supply from the VBuf line (which is 3.6V), but from the real 5V line. I have found that using VBuf made the system unstable as the larger RAM needs much more power. Also my prototype board required a separate MLC bypass capacitor soldered between the Pins 16 and 32 of the RAM IC.
    warn The RS232 problems noted in 3.0B may still be there as I did not change anything. Might be a problem with the power supply though, see RAM chip discussion above.
    msg The TTL parts mainly consist of the 'ALS (advanced Low-Power Shottky) TTL types, except where available.

    Files

    desc csa_bios_v3.0b-desc.txt
    schem csa_bios_v30d.sch
    schem csa_bios_v3.0d_sch.png
    layout csa_bios_v3.0d.brd
    layout csa_bios_v3.0d_brd.png

    Version: 3.0C

    Status: ok (for 32k RAM)

    Notes

    msg I have found stability problems with the 512k RAM version. Looking into the datasheet of the used RAM it says that Ax must be stable while /WE is low - so I gated /WE with Phi2. Didn't help though, see version 3.0D.

    Files

    schem csa_bios_v3.0c.sch
    schem csa_bios_v3.0c_sch.png
    layout csa_bios_v3.0c.brd
    layout csa_bios_v3.0c_brd.png

    Version: 3.0B

    Status: ok (for 32k RAM)

    Notes

    msg This is the new version of the board, using larger (up to 512k) RAM and ROM sockets. For this board also Eagle(tm) schematics and layout files are available
    warn The RS232 functionality works, although it seems larger capacitors for the RS232 voltage generation could be needed, as my test board looses characters. The same schematics works fine in the Gecko board, though.
    msg The TTL parts mainly consist of the 'ALS (advanced Low-Power Shottky) TTL types, except where available.

    Files

    desc csa_bios_v3.0b-desc.txt
    parts csa_bios_v3.0b-parts.txt
    schem csa_bios_v3.0b.sch
    schem csa_bios_v3.0b-sch.png
    layout csa_bios_v3.0b.brd
    layout csa_bios_v3.0b-lay.png
    photo csa_bios_v3.0b.jpg

    Version: 2.0B

    Status: ok

    Notes

    msg This is the old version of the board, using small (up to 32k) RAM and ROM sockets.

    Files

    schem csabios2.png
    schem csabios2.ps.gz
    desc csabios2desc.txt
    parts csabios2parts.txt
    photo csabios2.jpg(The ROM is currently missing)

    Version: 1.x

    Status: ok

    Notes

    stop This is the very first version, using an ACIA for the serial interface. It is (here) only documented as a photo.

    Files

    photo csabios.jpg

    Block diagram

    block diagram

    This diagram shows an overview on the board architecture