DRVIO board

This board implements a shugart bus interface as used in the standard PC floppy disk drives (5.25" and 3.5") in a way that is compatible with the Commodore VC1581 disk drive. I.e. it is planned that this board, together with the PETCPU board, make up a VC1581 replacement.

To accomodate this, the ICs can be addressed either via the bus I/O area, or via a mapping into the 1Mbyte bus memory address space - so it can mimick the 1581 address space.

Additionally, the board contains a Commodore IEC bus interface, as well as an infrared signal generator.

News:

2006-11-26 Published the board

Table of content

Driver
- PETCPU test
Board Revisions
- 1.1A (ok)
- 1.0B (prototype)
- 1.0A (prototype with bugs)

Driver

PETCPU test

This file includes a small test program that does a "readaddress" command on the WDC and either prints the sector header (in reverse) or the WDC status register in case of an error.

This driver runs on a PETCPU with the Commodore PET ROMs (just 'dL"test1"' :-) and expects the card I/O at $E8A0 (WD177x) and $E8B0 (CIA).

test2.tar.gz

Board revisions

Version: 1.1A

Status: ok

Notes

These are the differences:

The infrared sender is removed
Fix pull-ups in the floppy interface
Add databus driver and own 16MHz oscillator
Re-org the control port, fix polarity of MTR and SEL signals, so all drives are off on reset
New layout

This version is (slightly) incompatible with the previous one due to changes in the SEL and MTR lines.

This board implements a (shugart-type i.e PC-type) floppy disk controller. The board has been tested with 3.5" PC disk drives with DD (double density disks)

Using this board with HD-drives (i.e. 1.44M 3.5" floppies overclocks the WDC1772 chip used in this board, as it is only specified for DD-disks (720k).

Here is a summary of the jumper settings:

Jumper	Description	Setting	Meaning	VC1581 setting	standard setting
JP1	I/O address selection	1-2	$E8A/$E8B	don't care	*
JP1	I/O address selection	2-3	$E8E/$E8F	don't care
JP2	16MHz source	1-2	Take 16MHz from Bus
JP2	16MHz source	2-3	Use on-board oscillator
JP3	VC1581 disk unit selection: 8 when no jumper set.	1-2	10	As fits your setup. I have 3-4 for device number 9	n/a
		3-4	9
		1-2,3-4	11
JP4	IEC bus reset	1-2	when set, reset IEC bus with bus reset.
JP5	TOD input selection	1-2	50Hz bus signal		n/a
		2-3	Phi2 input (VC1581 setting for WD1770)
		not equiped	No input (VC1581 setting for WD1772)	*
JP6	DD/HD selection	1-2	Double density disks (DD) only	*
JP6	DD/HD selection	2-3	Double/High density (DD/HD) selection via control port		*
JP7	n/a
JP8	4k/8k Memory selection	1-2	$4*/$6*		n/a
JP8	4k/8k Memory selection	2-3	$4*+$5/$6+$7*	*	n/a
JP9	Memory mapped address selection	1-2	$54*/$56*
		3-4	$34*/$36*	*
		5-6	$04*/$06*
		7-8	no memory mapping		*

Files

	csa_drvio_v1.1a.sch
	csa_drvio_v1.1a-sch.png
	csa_drvio_v1.1a.brd
	csa_drvio_v1.1a-brd.png
	petcpudrv.jpg(Picture of setup with PETCPU system. Boards from left to right: DRVIO, PETCPU, PETIO, VDC)
	vc1581drv.jpg(Picture of setup as VC1581 together with PETCPU board.)

Version: 1.0B

Status: prototype

Notes

The layout has not been tested, only the schematics has been implemented by modifying my Rev.A board to Rev.B. The differences are:

The infrared sender is off after reset (reversed signal polarity)
Moved the INTR and DRQ lines to bits 7 and 6 respectively on the control port
The HD/DD selection is now made via control port and defaults to DD after reset.
The drive select signals are switched, to enable drive 0 (SELA) on reset, that is controlled by the VC1581 (via MTR A).
ATN can be pulled low via control port, so the board can be used as IEC controller (off after reset)
A 47k resistor between CIA pin 3 (PA1) and GND, to simulate a drive ready.

This board implements a (shugart-type i.e PC-type) floppy disk controller. The board has been tested with 3.5" PC disk drives with DD (double density disks)

Using this board with HD-drives (i.e. 1.44M 3.5" floppies overclocks the WDC1772 chip used in this board, as it is only specified for DD-disks (720k).

Here is a summary of the jumper settings:

Jumper	Description	Setting	Meaning	VC1581 setting	standard setting
JP1	I/O address selection	1-2	$E8A/$E8B	don't care	*
JP1	I/O address selection	2-3	$E8E/$E8F	don't care
JP2	n/a
JP3	VC1581 disk unit selection: 8 when no jumper set.	1-2	10	As fits your setup. I have 3-4 for device number 9	n/a
		3-4	9
		1-2,3-4	11
JP4	IEC bus reset	1-2	when set, reset IEC bus with bus reset.
JP5	TOD input selection	1-2	50Hz bus signal		n/a
		2-3	Phi2 input (VC1581 setting for WD1770)
		not equiped	No input (VC1581 setting for WD1772)	*
JP6	DD/HD selection	1-2	Double density disks (DD) only	*
JP6	DD/HD selection	2-3	Double/High density (DD/HD) selection via control port		*
JP7	Connector for infrared LEDs.
JP8	4k/8k Memory selection	1-2	$4*/$6*		n/a
JP8	4k/8k Memory selection	2-3	$4*+$5/$6+$7*	*	n/a
JP9	Memory mapped address selection	1-2	$54*/$56*
		3-4	$34*/$36*	*
		5-6	$04*/$06*
		7-8	no memory mapping		*

Files

	csa_drvio_v1.0b.sch
	csa_drvio_v1.0b-sch.png
	csa_drvio_v1.0b.brd
	csa_drvio_v1.0b-brd.png
	petcpudrv.jpg(Picture of setup with PETCPU system. Boards from left to right: DRVIO, PETCPU, PETIO, VDC)
	petcpujump.jpg(Jumper settings for PETCPU setting)
	vc1581drv.jpg(Picture of setup as VC1581 together with PETCPU board.)

Version: 1.0A

Status: prototype with bugs

Notes

	This board is superseded by the 1.0B version and will not be supported by any drivers.
	The drive select signals are driven the wrong way round. I.e. in a VC1581 setup after reset, the wrong drive is selected and the drive would not work.
	This board implements a (shugart-type i.e PC-type) floppy disk controller. The board has been tested with 3.5" PC disk drives with DD (double density disks)
	Using this board with HD-drives (i.e. 1.44M 3.5" floppies overclocks the WDC1772 chip used in this board, as it is only specified for DD-disks (720k).
	I found that modern 3.5" disk drives do not drive the DENSEL shugart bus signal (and not need it either). Thus the selection of HD/DD disks will change from shugart bus drive to I/O port driven.
	The Infrared signal generation will be changed to a NE555 based solution. Signal polarity may change, as it is currently enabled after reset.
	The board lacks a feature to drive the ATN line - so it cannot be used as a IEC bus master. This feature will be added if possible.

Files

	csa_drvio_v1.0a.sch
	csa_drvio_v1.0a-sch.png
	csa_drvio_v1.0a.brd
	csa_drvio_v1.0a-brd.png

Last modified: 2006-11-26.

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