CS/A bus connector

The bus layout is:

        a       c
--------------------------
    GND a    1  c GND
   Vbuf a    2  c Vcc
   50Hz a    3  c Vcc
 -IOINH a    4  c A19
 -EXTIO a    5  c A18
-MEMSEL a    6  c A17
 -IOSEL a    7  c A16
    -BE a    8  c A15
        a    9  c A14
        a   10  c A13
        a   11  c A12
        a   12  c A11
        a   13  c A10
        a   14  c A9
     D7 a   15  c A8
     D6 a   16  c A7
     D5 a   17  c A6
     D4 a   18  c A5
     D3 a   19  c A4
     D2 a   20  c A3
     D1 a   21  c A2
     D0 a   22  c A1
   -NMI a   23  c A0
   -IRQ a   24  c SYNC
    -SO a   25  c R/-W
    RDY a   26  c Phi2
   -RES a   27  c Phi1
    GND a   28  c Phi0
    GND a   29  c 2Phi2
    GND a   30  c 16MHz
    GND a   31  c 8Phi2
    GND a   32  c GND

Comments

• For non-MMU systems like the Gecko only the lines A0-A11, D0-D7, Phi2, R/-W, -RES, -IRQ, -NMI, -IOSEL are necessary. Still some of the other lines need to be taken care of. (-MEMSEL must be pushed high).
• -MEMSEL and -IOSEL are memory selection lines. If -MEMSEL goes low (active), address lines A0-A19 must be valid. If -IOSEL goes low, then only address lines A0-A11 must be valid. Both lines are not open collector lines (although this is one of the few 'known bugs' of this design)! The select lines are generated by the CPU. To map the I/O address space somewhere else (i.e. in a memory area selected by -MEMSEL), -EXTIO must be pulled low when an address in the selected area is accessed (by a memory card). Thus -MEMSEL and -IOSEL go then low on such an access.
  In MMU systems, the I/O space is normally mapped to some fixed location in the CPU address space and cannot be mapped around with the MMU. To avoid this mapping, -IOINH must be pulled low. Warning: if you pull -IOINH and not do not assign -EXTIO at some address, you lose access to the I/O area. In the BIOS card for the MMU system, a control port can set these lines. -IOINH and -EXTIO are open collector lines.
• Vbuf is a battery buffered 5 Volt supply. Vcc is standard 5 Volt supply, respective to GND.
• 50Hz is a 50/50 phase 50 Hz TTL signal, generated from line frequency. (In the U.S., you might generate it differently).
  16MHz is a 16 MHz clock.
• To drive some circuits synchronously with the CPU, there are 2Phi2 and 8Phi2. 2Phi2 has double the frequency than the CPU clock Phi2. At each transition of Phi2, 2Phi2 has a low-high transition. The high-low transition follows about less than 100 ns later. I use 2Phi2 to directly drive the -RAS signal of dynamic RAM.
  8Phi2 is the 8-times Phi2, but this signal has no fixed phase relation to Phi2. I use it as pixel clock in a video card.
  Both signals are usually generated by the CPU card.
• -BE cuts the CPU off the bus, i.e. select (-IOSEL, -MEMSEL), Data (D0-7) and Address lines (A0-A19) are put into tri-state. This line is asynchronous and should only be assigned with carefully designed circuitry using -RDY stop the CPU and Phi2 for clock and all that. Using -RDY and BE should allow an external bus master to take the bus, although it has not been tested so far.
• The lines that are not used (a9-a14) are reserved for future use.