CS/A65 RAMDisk

This board uses the (now outdated) 30-pin SIMM memory modules to build a RAM disk with up to 16Mbyte. The memory is accessible via a single register, using an auto-increment byte address counter (8-bit byte address within page only).

Two major board versions are available. The first one is more a concept and is built from TTL logic glue. The second one uses a CPLD to implement the DRAM controller.

The CPLD board is brand new and undergoing tests. With version 2.0E the power glitch has been fixed - the '245 driver was activated too early so it reached into the previous refresh cycle. The board works stable at 1MHz bus frequency, with 4 DRAM modules. At 2MHz write timing is stable, but there are read glitches (repeated reads vary). On the scope the signals look fine, from timing and shape, and seem to work for writing, so I am investigating bus terminators for the main system bus now.

The current status of the TTL board is that it works in some specific configurations. I built the board over two years ago and encountered a number of errors (see notes below). Only recently I have tested it with the 65816 CPU board, where it works with 3 modules with 1MByte each, but not 4 modules. I still have to retest with other CPU boards and 3 modules only.

Further tests still have to be performed, but I am not sure how far I will go into this with this design version. I had a discussion with Bil Herd - yes, the designer of the Commodore 128 - who suggested some improvements:

The new CPLD-based ramdisk board.

• Use a state machine and a GAL to create a simple DRAM controller and not rely on gate delay times to create signals. I found the 8296 timing signal generation a good example for such a system.
• The board layout used could use some improvements in the layout of the power supply lines, but also the address and data lines.
• The board lacks series resistors, and termination resistors, so signal reflections could easily be a problem.
• The /RAS signal is always sent to all modules - on a CPU read or write cycle only the active module needs it. This could be a reason for the problems below, which are possibly power supply related and if all modules draw power at the same time the actual access might fail.
• Maybe even use an FPGA to implement a DRAM controller

See the this page for the full discussion

The CPLD-based design for this board reflects these discussions.