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CS/A65 CPU

This board implements the main 6502 CPU board. It extends the 6502 cpu with a memory management unit (MMU) to achieve a 1 MByte address space. The board also contains the reset circuit, addressing logic for the I/O address space, clock and dRAM signal generation (2Phi2), bus drivers, and - in the newer versions - bus error detection circuits.

Table of content

  • Board Revisions
  • 2.0H (prototype)
  • 2.0G (prototype with bugs)
  • 1.3B (ok)
  • 1.2C (ok)
    •
  • Block diagram
    •

    Board revisions

    Version: 2.0H

    Status: prototype

    Notes

    msg Version 2.0H implements all the features mentioned above. There is an Eagle(tm) schematics and also layout available. The schematics and layout are not yet tested in a prototype board.
    warn This board has not yet been tested.
    msg The TTL types are mostly 'ALS technology, which is faster and less power-hungry than 'LS. In one place, however, I needed to fall back to 'LS: IC3 is still a 74LS245 instead of a 74ALS245, as it seemed that the 6522 on the PETIO board did not like it. Don't ask me why, I don't know.
    msg This board implements new features, in that bus errors like writing on a write protected page, accessing a page that is not mapped, and also fetching an opcode from a "no-execute" page! This feature is similar to the new feature implemented in the PC processors, to protect from buffer overflows.

    Files

    desc csa_cpu_v2.0h-desc.txt
    parts csa_cpu_v2.0h-parts.txt
    schem csa_cpu_v2.0h.sch
    schem csa_cpu_v2.0h-sch.png
    layout csa_cpu_v2.0h.brd
    layout csa_cpu_v2.0h-lay.png

    Version: 2.0G

    Status: prototype with bugs

    Notes

    msg Version 2.0G implements all the features mentioned above. There is an Eagle(tm) schematics and also layout available. The schematics and layout are tested in a prototype board.
    warn This version has a severe bug (that can be fixed, though): the mmu inputs RS0-RS3 are connected to the BUSA0-BUSA3 in the wrong order. Due to the way the address bits are connected, it should have RS0 connected to BUSA3 and so on.

    Files

    schem csa_cpu_v2.0g.sch
    schem csa_cpu_v2.0g-sch.png
    layout csa_cpu_v2.0g.brd
    layout csa_cpu_v2.0g-lay.png
    photo csa_cpu_v2.0g.jpg(Without CPU, to see the driver underneath)

    Version: 1.3B

    Status: ok

    Notes

    msg This version implements an additional write protection circuit. I.e. an additional mmu bit is used to disable the memory access to the selected memory.
    warn This schematics is only available as a "diff" to the 1.2C version.

    Files

    desc cpu65wpdesc.txt
    schem cpu65wp.png
    schem cpu65wp.fig
    schem cpu65wp.ps.gz

    Version: 1.2C

    Status: ok

    Notes

    msg This is the original cpu board. It implements most features, but not the bus error detection circuits.

    Files

    desc cpu65desc.txt
    parts cpu65parts.txt
    schem cpu65.png
    schem cpu65.fig
    schem cpu65.ps.gz
    photo cpu65.jpg(The IC on top and the 74LS244 on the right are testbeds for the new 2Phi2 generation and the write protect as implemented in newer versions)

    Block diagram

    block diagram

    Block diagram of the cpu board. It shows the MMU, but also the port to read the CPU address. Please note that the MMU and the port can be accessed from the bus alone, if the cpu is decoupled from the bus with the drivers. This can be used when the cpu is stopped with the RDY e.g. by a bus error.