Blitter - how it works

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  2010-09-17 Started this page

• Architecture
• • Address Generation
• Operating Modes

The blitter architecture is based on a CPU-like architecture. It uses registers connected to shared busses, and a single ALU between the busses.

Blitter architecture (click to enlarge)

The main components are:

• Address generation: creates the blitter addresses to read and write the data bytes.
• Data transfer register: The register to store the data read in the first transfer cycle, and to provide it in the second cycle
• Counter register: counts down the number of bytes to transfer. Also compares the number of bytes to zero, to get an end signal.
• Control: state control, and a logic array to control all the registers and buffers

Address Generation

Blitter address generation (click to enlarge)

The address generation components are:

• LDADDR/STADDR: address registers for load and store addresses
• LDINC/STINC: registers for address increment
• ALU: Adder to add the address and the increment
• ZERO: zero increment (see below for the purpose)
• Address data buffer: connects the INBUS to the CPU data bus. Note that this is actually three 8-bit buffers, where one byte at a time can be accessed (denoted by the "8Bit" in the diagram)
• Increment data buffer: connects the Increment bus to the CPU data bus
• Address buffer: drives the address from OUTBUS to the system address bus

These components are connected together by three busses:

• INBUS: The INBUS is called that as it feeds a new address value into the load and store address registers. The value can come from the ALU output or from the CPU data bus.
• OUTBUS: The outbus holds the output from the load and store address registers. Its value is put on the actual address bus during a fetch or store operation. The value from this bus is at the same time also fed into one side of the ALU adder.
• Increment: This bus holds the output of the increment registers, resp. the zero increment value. Its value is fed into the second ALU adder input, but can also be read from the CPU data bus.

Together these components allow to do the actual data transfer, as well as the address increment of the address registers in a single cycle. The same, shared, ALU and bus components are used in both cases, when the data is fetched and when it is stored. This helps to keep the required board space small enough.

The actual circuit also features a control register, that allows to set the adder's carry, and the additional bits necessary to extend the increment value to a full address width. This for example allows:

• incrementing 256 byte (page): set the carry and use an increment value of $ff
• decrementing: set the carry, use inverse (EOR #$FF) of the value to subtract as increment and set the complement bit (upper increment bits). For example to substract by one, set the carry, use $FE as increment value and setting the complement makes the increment to $FFFFE. You can also clear the carry and use $FFFFF as increment of course.

This section explains the operating modes of the address generation.

Mode	diagram (click to enlarge)
CPU write address. The CPU data bus is directly fed into the load and store address registers via the INBUS
CPU read address. Please note that the address is actually taken from the INBUS, which is the output of the ALU, not of the address register. If the data bus were connected to the address register output, it would require three (for up to 24 address bits) 8-bit drivers. Using the ALU output allows to reuse the data bus drivers used to write the address registers, and only requires a zero input to the ALU increment input - so that the address register value is passed through the ALU unchanged.
CPU write increment. Similar to writing the addresses, the increment registers are directly fed from the CPU data bus.
CPU read increment. To read the increment, a separate read pass-buffer is used. As both increment registers output to the same bus, only a single pass-buffer is used for both increment registers.
Blitter read/write data. The output of the address register is passed through to the system address bus. But this value is also passed to one input of the adder ("ALU"). The other input of the adder is fed from the increment register. Thus the adder output presents the next value for the address register. So at the end of the cycle this new addres is latched into the address register.